Signal Selecting Circuit and Recording Medium Having Program Recorded Thereon

ABSTRACT

A signal selecting circuit is disclosed which outputs a first and a second digital signals by converting a first and a second analog signals into digital signals, the first and the second analog signals being the same or different signals selected from a plurality of analog signals, the signal selecting circuit comprising: an analog signal selection circuit that, based on an analog selection signal, selects the first and the second analog signals from the plurality of analog signals; a first AD converter that converts the first analog signal outputted from the analog signal selection circuit into a third digital signal to output the third digital signal; a second AD converter that converts the second analog signal outputted from the analog signal selection circuit into a fourth digital signal to output the fourth digital signal; a digital signal selection circuit that, based on a digital signal, selectively outputs one or both of the third and the fourth digital signals as the first and the second digital signals; and a control circuit that, based on an output selection signal for selecting the first and the second digital signals, outputs the analog selection signal and the digital selection signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of priority to Japanese PatentApplication No. 2005-361323, filed Dec. 15, 2005, of which full contentsare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a signal selecting circuit and arecording medium having a program recorded thereon.

2. Description of the Related Art

In recent car audio systems, music or voices from different soundsources have come to be outputted separately to front speakers and rearspeakers (see, e.g., Japanese Patent Application Laid-open PublicationNo. 2005-223505). In such car audio systems, an analog selector hasoften been used for selecting sound sources to be outputted separatelyto the front speakers and the rear speakers from among a plurality ofsound sources (analogue signals) such as a CD, an MD, and a radio.

FIG. 14 depicts a common example of the configuration of the analogselector for selecting sound sources to be outputted separately to thefront speakers and the rear speakers. An analog selector 201 serves toselect a sound source outputted to the front speakers and includesswitches 211 and 212, resistors 213 to 215, and an operational amplifier216. An analog selector 221 serves to select a sound source outputted tothe rear speakers and includes switches 231 and 232, resistors 233 to235, and an operational amplifier 236. Input signals A and B are fed asselectable sound sources to each of the analog selectors 201 and 221.For example, by turning the switch 211 on and the switch 212 off, theswitch 231 off, and the switch 232 on, the input signal A is provided asoutput (analog output 1) to the front speakers and the output signal Bis provided as output (analog output 2) to the rear speakers.

In this manner, use of the analog selectors 201 and 221 enables music orvoices from different sound sources to be outputted separately to thefront speakers and the rear speakers.

In the configuration of FIG. 14, however, when the same sound source asbeing selected by one of the front and the rear is selected by theother, the one not changing the sound source undergoes occurrence of aswitching noise. Assume for example that the switches 211, 212, 231, and232 are on, off, off, and on, respectively, so that the input signals Aand B are provided as the analog outputs 1 and 2, respectively. It isfurther assumed that the switches 231 and 232 are turned on and off,respectively, to switch the signal provided as the analog output 2 tothe input signal A provided as the analog output 1. At that time, aswitching noise occurs due to the switch 231 on and propagates to theswitch 211. Therefore, when the rear selects the same sound source asthe front does, a nose will occur in the analog output 1 provided to thefront speakers though the front does not change the sound source.Similarly, when the front selects the same sound source as the reardoes, a nose will occur in the analog output 2 provided to the rearspeakers though the rear does not change the sound source.

SUMMARY OF THE INVENTION

The present invention was conceived in view of the above problems and itis therefore the object of the present invention to provide a signalselecting circuit issuing a plurality of output signals selected andconverted from a plurality of analog signals inputted, the circuit whenchanging an output signal, preventing a noise from occurring in anotheroutput signal unchanged.

In order to achieve the above object, according to an aspect of thepresent invention there is provided a signal selecting circuitoutputting a first and a second digital signals by converting a firstand a second analog signals into digital signals, the first and thesecond analog signals being the same or different signals selected froma plurality of analog signals, the signal selecting circuit comprising:an analog signal selection circuit that, based on an analog selectionsignal, selects the first and the second analog signals from theplurality of analog signals; a first AD converter that converts thefirst analog signal outputted from the analog signal selection circuitinto a third digital signal to output the third digital signal; a secondAD converter that converts the second analog signal outputted from theanalog signal selection circuit into a fourth digital signal to outputthe fourth digital signal; a digital signal selection circuit that,based on a digital selection signal, selectively outputs one or both ofthe third and the fourth digital signals as the first and the seconddigital signals; and a control circuit that, based on an outputselection signal for selecting the first and the second digital signals,outputs the analog selection signal and the digital selection signal.

When the control circuit receives the output selection signal forchanging the second digital signal to the same signal as the firstdigital signal, in a state where the third digital signal is outputtedas the first digital signal and where the fourth digital signal isoutputted as the second digital signal, the control circuit may outputthe digital selection signal for outputting the third digital signal asthe first and the second digital signals.

When the control circuit receives the output selection signal forchanging the first digital signal to a signal different from the seconddigital signal, in a state where the third digital signal is outputtedas the first and the second digital signals, the control circuit mayoutput the analog selection signal for selecting as the second analogsignal an analog signal corresponding to the first digital signalindicated by the output selection signal, without changing the firstanalog signal.

When the control circuit receives the output selection signal forchanging the first digital signal to the same signal as the seconddigital signal, in a state where the third digital signal is outputtedas the second digital signal and where the fourth digital signal isoutputted as the first digital signal, the control circuit may outputthe digital selection signal for outputting the third digital signal asthe first and the second digital signals.

When the control circuit receives the output selection signal forchanging the first digital signal to a signal different from the seconddigital signal, in a state where the third digital signal is outputtedas the second digital signal and where the fourth digital signal isoutputted as the first digital signal, the control circuit may outputthe analog selection signal for selecting as the second analog signal ananalog signal corresponding to the first digital signal indicated by theoutput selection signal, without changing the first analog signal.

When the control circuit receives the output selection signal forchanging the second digital signal to a signal different from the firstdigital signal, in a state where the third digital signal is outputtedas the first and the second digital signals, the control circuit mayoutput: the analog selection signal for selecting as the second analogsignal an analog signal corresponding to the second digital signalindicated by the output selection signal, without changing the firstanalog signal; and the digital selection signal for outputting the thirddigital signal as the first digital signal and outputting the fourthdigital signal as the second digital signal.

When the control circuit receives the output selection signal forchanging the first digital signal to a signal different from the seconddigital signal, in a state where the third digital signal is outputtedas the first digital signal and where the fourth digital signal isoutputted as the second digital signal, the control circuit may outputthe analog selection signal for selecting as the first analog signal ananalog signal corresponding to the first digital signal indicated by theoutput selection signal.

When outputting the digital selection signal for outputting the thirddigital signal as the first and the second digital signals, the controlcircuit may power down an operation of the second AD converter.

In order to achieve the above object, according to another aspect of thepresent invention there is provided a recording medium having a programrecorded thereon, the program causing a processor of a signal selectingcircuit which includes the processor that performs control foroutputting a first and a second digital signals by converting a firstand a second analog signals into digital signals, the first and thesecond analog signals being the same or different signals selected froma plurality of analog signals, an analog signal selection circuit that,based on an analog selection signal, selects the first and the secondanalog signals from the plurality of analog signals, a first ADconverter that converts the first analog signal outputted from theanalog signal selection circuit into a third digital signal to outputthe third digital signal, a second AD converter that converts the secondanalog signal outputted from the analog signal selection circuit into afourth digital signal to output the fourth digital signal, a digitalsignal selection circuit that, based on a digital selection signal,selectively outputs one or both of the third and the fourth digitalsignals as the first and the second digital signals, and a memory thatstores a state of selection of the third and the fourth digital signalsin the digital signal selection circuit, to execute the steps of:accepting an output selection signal for selecting the first and thesecond digital signals; outputting the analog selection signal and thedigital selection signal based on the output selection signal acceptedand on the state of selection stored in the memory; and updating thestate of selection stored in the memory.

The program may cause the processor to execute the steps of: whenaccepting the output selection signal for changing the second digitalsignal to the same signal as the first digital signal, in a state wherethe third digital signal is outputted as the first digital signal andwhere the fourth digital signal is outputted as the second digitalsignal, outputting the digital selection signal for outputting the thirddigital signal as the first and the second digital signals; and updatingthe state of selection stored in the memory.

The program may cause the processor to execute the steps of: whenaccepting the output selection signal for changing the first digitalsignal to a signal different from the second digital signal, in a statewhere the third digital signal is outputted as the first and the seconddigital signals, outputting the analog selection signal for selecting asthe second analog signal an analog signal corresponding to the firstdigital signal indicated by the output selection signal, withoutchanging the first analog signal; and updating the state of selectionstored in the memory.

The program may cause the processor to execute the steps of: whenaccepting the output selection signal for changing the first digitalsignal to the same signal as the second digital signal, in a state wherethe third digital signal is outputted as the second digital signal andwhere the fourth digital signal is outputted as the first digitalsignal, outputting the digital selection signal for outputting the thirddigital signal as the first and the second digital signals; and updatingthe state of selection stored in the memory.

The program may cause the processor to execute the step of, whenaccepting the output selection signal for changing the first digitalsignal to a signal different from the second digital signal, in a statewhere the third digital signal is outputted as the second digital signaland where the fourth digital signal is outputted as the first digitalsignal, outputting the analog selection signal for selecting as thesecond analog signal an analog signal corresponding to the first digitalsignal indicated by the output selection signal, without changing thefirst analog signal.

The program may cause the processor to execute the steps of: whenaccepting the output selection signal for changing the second digitalsignal to a signal different from the first digital signal, in a statewhere the third digital signal is outputted as the first and the seconddigital signals, outputting the analog selection signal for selecting asthe second analog signal an analog signal corresponding to the seconddigital signal indicated by the output selection signal, withoutchanging the first analog signal, and the digital selection signal foroutputting the third digital signal as the first digital signal andoutputting the fourth digital signal as the second digital signal; andupdating the state of selection stored in the memory.

The program may cause the processor to execute the step of, whenaccepting the output selection signal for changing the first digitalsignal to a signal different from the second digital signal, in a statewhere the third digital signal is outputted as the first digital signaland where the fourth digital signal is outputted as the second digitalsignal, outputting the analog selection signal for selecting as thefirst analog signal an analog signal corresponding to the first digitalsignal indicated by the output selection signal.

The program may cause the processor to execute the step of outputting asignal for powering down an operation of the second AD converter, whenoutputting the digital selection signal for outputting the third digitalsignal as the first and the second digital signals.

The above and other features of the present invention will become moreapparent from the following description of this specification togetherwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

For thorough understanding of the present invention and advantagesthereof, the following description should be read in conjunction withthe accompanying drawings, in which:

FIG. 1 depicts an exemplary configuration of a vehicle-mounted audioreproduction circuit configured to include a signal selecting circuitaccording to an embodiment of the present invention;

FIG. 2 depicts a first state of selection;

FIGS. 3A and 3B depict a second state of selection;

FIG. 4 depicts a third state of selection;

FIG. 5 depicts transitions in the states of selection of a digitalselector;

FIG. 6 is a block diagram of an exemplary configuration of a controlcircuit;

FIG. 7 is a circuit diagram of an exemplary configuration of a selectionsignal comparing circuit;

FIG. 8 is a circuit diagram of an exemplary configuration of a statemachine circuit;

FIG. 9 depicts an exemplary configuration of a decode circuit A;

FIG. 10 depicts an exemplary configuration of a decode circuit B;

FIG. 11 is a timing chart of an exemplary operation of the controlcircuit;

FIG. 12 depicts an exemplary configuration of the control circuit incase of providing a program-based control for the signal selectingcircuit;

FIG. 13 is a flowchart of operations of the control circuit; and

FIG. 14 depicts a common configuration example of an analog selector forselecting sound sources to be outputted to front speakers and rearspeakers.

DETAILED DESCRIPTION OF THE INVENTION

At least the following details will become apparent from descriptions ofthis specification and of the accompanying drawings.

==Overall Configuration==

FIG. 1 depicts an exemplary configuration of a vehicle-mounted audioreproduction circuit configured to include a signal selecting circuitaccording to an embodiment of the present invention. The vehicle-mountedaudio reproduction circuit generally designated at 1 includes the signalselecting circuit designated at 10, a microcontroller interface(microcontroller I/F) 11, a digital signal processor (DSP) 12, and a DAconverters (DACs) 13 and 14.

The vehicle-mounted audio reproduction circuit 1 is a circuit thatselects an analog signal (front output) to be outputted to frontspeakers and an analog signal (rear output) to be outputted to rearspeakers from a plurality of analog signals (inputs 0 to 3 in thisexample) inputted from sound sources such as a CD, an MD, and a radio inaccordance with instructions from a microcontroller 21.

A control signal from the microcontroller 21 is fed via themicrocontroller I/F 11 to the signal selecting circuit 10. The controlsignal is capable of specifying which sound sources to be provided asthe front output and the rear output, respectively. For example, thecontrol signal is capable of specifying the input 0 (e.g., the CD) asthe front output and the input 2 (e.g., the radio) as the rear output.Based on the control signal, the signal selecting circuit 10 issues asignal (first digital signal) 15 that is obtained by digitallyconverting a sound source selected as the front output and a signal(second digital signal) 16 that is obtained by digitally converting asound source selected as the rear output.

The first digital signal 15 fed from the signal selecting circuit 10 issubjected to an audio process, etc., by the DSP 12 and then is convertedinto an analog signal by the DAC 13 to be provided as the front output.In the same manner, the second digital signal 16 fed from the signalselecting circuit 10 is subjected to an audio process, etc., by the DSP12 and then is converted into an analog signal by the DAC 14 to beprovided as the rear output.

The configuration of the signal selecting circuit 10 will hereinbelow bedescribed. The signal selecting circuit 10 includes analog selectors 31and 32, AD converters (ADCs) 33 and 34, a digital selector 35, and acontrol circuit 36. The analog selectors 31 and 32 correspond to ananalog signal selecting circuit of the present invention. The ADCs 33and 34 correspond to a first and a second AD converters, respectively,of the present invention. The digital selector 35 corresponds to adigital signal selecting circuit of the present invention.

A plurality of analog signals (inputs 0 to 3 in this example) are fed assound sources to the analog selector 31 (a first analog signal selectingcircuit), any one (a first analog signal) of which analog signals isselected for output based on a control signal FCO (a first selectionsignal) fed from the control circuit 36. The same analog signals (theinputs 0 to 3 in this example) are fed also to the analog selector 32 (asecond analog signal selecting circuit), any one (a second analogsignal) of which analog signals is selected for output based on acontrol signal RCO (a second selection signal) fed from the controlcircuit 36. Although in this example exactly the same signals are fed toboth the analog selectors 31 and 32, at least one common analog signalneeds only to be fed thereto. For example, the inputs 0 and 1 may be fedto the analog selector 31, while the inputs 0, 2 and 3 may be fed to theanalog selector 32. The control signals FCO and RCO correspond to ananalog selection signal of the present invention.

The ADC 33 converts the analog signal (the first analog signal) fed fromthe analog selector 31 into a digital signal (a third digital signal)for output. Similarly, the ADC 34 converts the analog signal (the secondanalog signal) fed from the analog selector 32 into a digital signal (afourth digital signal) for output. A control signal FPD fed from thecontrol circuit 36 is fed to the ADC 33, while a control signal RPD fromthe control circuit 36 is fed to the ADC 34. In case of the controlsignal FPD being 1, the operation of the ADC 33 is powered down whereasin case of the control signal RPD being 1, the operation of the ADC 34is powered down.

The third and the fourth digital signals from the ADCs 33 and 34,respectively, are fed to the digital selector 35 so that based oncontrol signals FSEL and RSEL (a digital selection signal) fed from thecontrol circuit 36 the digital selector 35 outputs either the third orthe fourth digital signal as the first digital signal 15 and as thesecond digital signal 16. More specifically, the digital selector 35includes selection circuits 41 and 42 receiving the third and the fourthdigital signals. The selection circuit 41 receives the control signalFSEL fed from the control circuit 36, and in case of the FSEL being 0,outputs the third digital signal fed from the ADC 33 as the firstdigital signal 15, but in case of the FSEL being 1, outputs the fourthdigital signal fed from the ADC 34 as the first digital signal 15. Theselection circuit 42 receives the control signal RSEL fed from thecontrol circuit 36, and in case of the RSEL being 0, outputs the fourthdigital signal fed from the ADC 34 as the second digital signal 16, butin case of the RSEL being 1, outputs the third digital signal fed fromthe ADC 33 as the second digital signal 16.

The control circuit 36 stores the states of selection of the analogselectors 31 and 32 and of the digital selector 35, and provides thecontrol signals FCO, RCO, FPD, RPD, FSEL, and RSEL as its outputs to therespective circuits based on a control signal for changing the frontoutput and the rear output fed via the microcontroller I/F 11.

Description will then be made of the state of selection of the digitalselector 35 in the signal selecting circuit 10. FIG. 2 depicts a firststate of selection. As shown, the selection circuit 41 outputs the thirddigital signal fed from the ADC 33 as the first digital signal 15, whilethe selection circuit 42 outputs the fourth digital signal fed from theADC 34 as the second digital signal 16. In this embodiment, the state ofselection shown in FIG. 2 is referred to as a normal state. In thenormal state, a sound source selected by the analog selector 31 isoutputted from the front speakers, while a sound source selected by theanalog selector 32 is outputted from the rear speakers.

FIGS. 3A and 3B depict a second state of selection. As shown in FIG. 3A,the selection circuit 41 outputs the fourth digital signal fed from theADC 34 as the first digital signal 15, while the selection circuit 42outputs the fourth digital signal fed from the ADC 34 as the seconddigital signal 16. Since the third digital signal fed from the ADC 33 isnot required in this case, the operation of the ADC 33 can be powereddown by setting the control signal FPD to 1 for example. In FIG. 3B onthe other hand, the selection circuit 41 outputs the third digitalsignal fed from the ADC 33 as the first digital signal 15, while theselection circuit 42 outputs the third digital signal fed from the ADC33 as the second digital signal 16. Since the fourth digital signal fedfrom the ADC 34 is not required in this case, the operation of the ADC34 can be powered down by setting the control signal RPD to 1 forexample. In this embodiment, the states of selection shown in FIGS. 3Aand 3B are referred to as a branch state. In the branch state, a soundsource selected by the analog selector 31 or 32 is outputted from thefront speakers and from the rear speakers.

FIG. 4 depicts a third state of selection. As shown, the selectioncircuit 41 outputs the fourth digital signal fed from the ADC 34 as thefirst digital signal 15, while the selection circuit 42 outputs thethird digital signal fed from the ADC 33 as the second digital signal16. In this embodiment, the state of selection shown in FIG. 4 isreferred to as a cross state. In the cross state, a sound sourceselected by the analog selector 32 is outputted from the front speakers,while a sound source selected by the analog selector 31 is outputtedfrom the rear speakers.

Description will then be made of the transitions in the states betweenthe normal state, the branch state, and the cross state. FIG. 5 depictsthe transitions in the states of selection of the digital selector. Inthis embodiment, the state of selection is represented by e.g., a 2-bitbinary number, with the normal state, the branch state, and the crossstate being represented as “00”, “11” and “01”, respectively.

When the initial state is the normal state, the control signals FSEL andRSEL are both 0 so that the third digital signal fed from the ADC 33 isoutputted as the first digital signal 15 and that the fourth digitalsignal fed from the ADC 34 is outputted as the second digital signal 16.Since the ADCs 33 and 34 are both in operation, the control signals FPDand RPD are 0. The state transitions are as follows when a controlsignal for changing either the front output or the rear output isreceived from the microcontroller 21 in the initial state. First, incase the sound source to be outputted to the changed side is differentfrom the sound source being outputted to the unchanged side, the stateof selection remains unchanged, i.e., in the normal state (transition1). On the contrary, in case the sound source to be outputted to thechanged side is the same as the sound source being outputted to theunchanged side, the state of selection transitions to the branch state(transition 2).

Since in the branch state the digital signal fed from the ADC 33 or 34is outputted as the first digital signal 15 and as the second digitalsignal 16, the control signals (FSEL, RSEL, FPD, RPD) result in either(1, 0, 1, 0) or (0, 1, 0, 1). In this manner, when the state ofselection is changed from the state where the front output and the rearoutput are different from each other (normal state) to the state wherethe front output and the rear output are the same (branch state), thechange of the sound source to be outputted is carried out by switchingthe digital selector 35 instead of switching the analog selectors 31 and32. That is, since the same sound source is not selected by the analogselectors 31 and 32, a noise attendant on the switching operation of oneof the analog selectors 31 and 32 will not propagate to the other.

The state transitions are as follows when a control signal for changingeither the front output or the rear output is received from themicrocontroller 21 in the branch state. First, in case the sound sourceoutputted to the unchanged side (the front or the rear) is the same asthe sound source being selected by the corresponding analog selector 31or 32, the state of selection transitions to the normal state(transition 3). On the contrary, in case the sound source beingoutputted to the unchanged side (the front or the rear) is differentfrom the sound source selected by the corresponding analog selector 31or 32, the state of selection transitions to the cross state (transition4).

More specifically, assume for example that a control signal for changingthe front output is received in the branch state of FIG. 3A. In such acase, the sound source being provided as the unchanged rear output isthe same as the sound source selected by the corresponding analogselector 32, thus transitioning to the normal state. On the other hand,assume for example that a control signal for changing the rear output isreceived in the branch state of FIG. 3A. In such a case, the soundsource being provided as the unchanged front output is different fromthe sound source selected by the corresponding analog selector 31, thustransitioning to the cross state. In this case, switching of the analogselector 32 is not carried out so that the sound source selected by theanalog selector 32 continues to be provided as the front output. Thus,by enabling the transition from the branch state to the cross state, aswitching noise will not occur on the side where the sound source is notchanged.

The state transitions are as follows when a control signal for changingeither the front output or the rear output is received from themicrocontroller 21 in the cross state. First, in case the sound sourceto be outputted to the changed side is different from the sound sourcebeing outputted to the unchanged side, the state of selection remainsunchanged, i.e., in the cross state (transition 5). On the contrary, incase the sound source to be outputted to the changed side is the same asthe sound source being outputted to unchanged side, the state ofselection transitions to the branch state (transition 2). In thismanner, when the state of selection is changed from the state where thefront output and the rear output are different from each other (crossstate) to the state where the front output and the rear output are thesame (branch state), the change of the sound source to be outputted iscarried out by switching the digital selector 35 instead of switchingthe analog selectors 31 and 32. That is, since the same sound source isnot selected by the analog selectors 31 and 32, a noise attendant on theswitching operation of one of the analog selectors 31 and 32 will notpropagate to the other.

==Control Circuit==

Description will then be made of the configuration of the controlcircuit 36 for implementing the state transitions as shown in FIG. 5.FIG. 6 is a block diagram of an exemplary configuration of the controlcircuit 36. The control circuit 36 is configured to include a selectionsignal comparing circuit 51, a state machine circuit 52, and a selectionsignal decode circuit 53.

The selection signal comparing circuit 51 receives a control signal sentfrom the microcontroller 21. Based on the control signal, the selectionsignal comparing circuit 51 issues signals N_FD, N_RD, cmpr_FD, cmpr_RD,cmpr_FRD, and change_mode.

The signal N_FD is a signal indicative of a sound source of the frontoutput changed and the signal N_RD is a signal indicative of a soundsource of the rear output changed.

The signal cmpr_FD is a signal indicative of a change of the frontoutput and which changes e.g., from low to high when the front output ischanged. The signal cmpr_RD is a signal indicative of a change of therear output and which changes from low to high when the rear output ischanged. The signal cmpr_FRD is a signal indicative of whether thechanged front output (N_FD) and the changed rear output (N_RD) are thesame or different and which is high if the signal N_FD and the signalN_RD are the same but low if they are different in this embodiment. Thesignal change_mode is a signal indicative of a change of either thefront output or the rear output and which changes e.g., from low to highwhen the front output or the rear output is changed.

The state machine circuit 52 causes the state of selection to transitionbased on the signals cmpr_FD, cmpr_FRD, and change_mode fed from theselection signal comparing circuit 51 and on signals cmpr_FDFCO andcmpr_RDRCO fed from the selection signal decode circuit 53, and issues asignal STATE indicative of the state of selection and a signal n_STATEused to determine the next state of selection.

The selection signal decode circuit 53 receives the signals change_mode,N_FD, and N_RD fed from the selection signal comparing circuit 51, aswell as the signal n_STATE fed from the state machine circuit 52. Inresponse to those signals, the selection signal decode circuit 53provides as its output the control signals FCO, RCO, FPD, RPD, FSEL, andRSEL for controlling the analog selectors 31 and 32, the ADCs 33 and 34,and the digital selector 35, respectively. The selection signal decodecircuit 53 consists of a decode circuit A 54 and a decode circuit B 55.

FIG. 7 is a circuit diagram of an exemplary configuration of theselection signal comparing circuit 51. The selection signal comparingcircuit 51 is configured to include a decode circuit 61, registers 62and 63, AND circuits 64 and 65, selecting circuits 66 and 67, XORcircuits 68 to 74, and NOR circuits 75 to 77.

The decode circuit 61 decodes a control signal fed from themicrocontroller 21 into e.g., a 2-bit selection signal, e.g., a 1-bitfront change enable signal, and e.g., a 1-bit rear change enable signal,for output. The selection signal is a signal for selecting the soundsource of the front output or the rear output, the selection signalhaving in two bits for example “00” to be set when selecting the input0, “01” for the input 1, “10” for the input 2, and “11” for the input 3.The front change enable signal is a signal indicative of an instructionto change the front output and is high only for one clock period forexample. Similarly, the rear change enable signal is a signal indicativeof an instruction to change the rear output and is high only for oneclock period for example.

The register 62 holds a signal D_FD indicative of the sound source ofthe front output before change. The selection signal issued from thedecode circuit 61 is fed to a data input of the register 62. The ANDcircuit 64 receives the front change enable signal and a clock signalCLK and provides its output to a clock input of the register 62. Sincethe front change enable signal is high only for one clock period of theclock signal CLK when the front output is changed, the selection signalfrom the decode circuit 61 is delivered to the register 62 at the timingwhen the clock signal CLK changes from low to high for example. Theregister 62 is comprised of a gated clock, and the signal D_FD changesat the next timing the clock signal CLK changes from low to high. On thecontrary, since the front change enable signal is low when the rearoutput is changed, the signal D_FD held in the register 62 remainsunchanged.

The register 63 holds a signal D_RD indicative of the sound source ofthe rear output before change. The selection signal issued from thedecode circuit 61 is fed to a data input of the register 63. The ANDcircuit 65 receives the rear change enable signal and the clock signalCLK and provides its output to a clock input of the register 63. Sincethe rear change enable signal is high only for one clock period of theclock signal CLK when the rear output is changed, the selection signalfrom the decode circuit 61 is delivered to the register 63 at the timingwhen the clock signal CLK changes from low to high for example. Theregister 63 is also comprised of the gated clock, and the signal D_RDchanges at the next timing the clock signal CLK changes from low tohigh. On the contrary, since the rear change enable signal is low whenthe front output is changed, the signal D_RD held in the register 63remains unchanged.

The selecting circuit 66 receives the selection signal fed from thedecode circuit 61 and the signal D_FD fed from the register 62. Theselecting circuit 66 further receives the front change enable signal asa signal for selecting either of those signals. The selecting circuit 66provides as its output the selection signal fed from the decode circuit61 when the front change enable signal is high (1), whereas it providesas its output the signal D_FD fed from the register 62 when the frontchange enable signal is low (0). A signal fed from the selecting circuit66 is designated at N_FD.

The selecting circuit 67 receives the selection signal fed from thedecode circuit 61 and the signal D_RD fed from the register 63. Theselecting circuit 67 further receives the rear change enable signal as asignal for selecting either of those signals. The selecting circuit 67provides as its output the selection signal fed from the decode circuit61 when the rear change enable signal is high (1), whereas it providesas its output the signal D_RD fed from the register 63 when the rearchange enable signal is low (0). A signal fed from the selecting circuit67 is designated at N_RD.

The XOR circuits 68 and 69, and the NOR circuit 75 are circuitscomparing the signal N_FD with the signal D_FD, the NOR circuit 75issuing the signal cmpr_FD indicative of the result of comparison. Inthis embodiment, the signal cmpr_FD goes high when the signals N_FD andD_FD are the same, whereas the signal cmpr_FD goes low when they aredifferent.

The XOR circuits 72 and 73, and the NOR circuit 77 are circuitscomparing the signal N_RD with the signal D_RD, the NOR circuit 77issuing the signal cmpr_RD indicative of the result of comparison. Inthis embodiment, the signal cmpr_RD goes high when the signals N_RD andD_RD are the same, whereas the signal cmpr_RD goes low when they aredifferent.

The XOR circuits 70 and 71, and the NOR circuit 76 are circuitscomparing the signal N_FD with the signal N_RD, the NOR circuit 76issuing the signal cmpr_FRD indicative of the result of comparison. Inthis embodiment, the signal cmpr_FRD goes high when the signals N_FD andN_RD are the same, whereas the signal cmpr_FRD goes low when they aredifferent.

The signals cmpr_FD and cmpr_RD are fed to the XOR circuit 74 which inturn provides the signal change_mode as its output. Thus, the signalchange_mode goes high only when either the signal cmpr_FD or the signalcmpr_RD is high.

FIG. 8 is a circuit diagram of an exemplary configuration of the statemachine circuit 52. The state machine circuit 52 is configured toinclude selection circuits 91 to 96, a register 97, and an AND circuit98.

The selection circuit 91 receives a 2-bit signal “11” indicative of thebranch state and a 2-bit signal “00” indicative of the normal state. Theselection circuit 91 further receives the signal cmpr_FRD as a signalfor selecting the output signal. For example, the selection circuit 91issues the signal “00” indicative of the normal state when the signalcmpr_FRD is low (0), whereas it issues the signal “11” indicative of thebranch state when the signal cmpr_FRD is high (1).

The selection circuit 92 receives the 2-bit signal “11” indicative ofthe branch state and a 2-bit signal “01” indicative of the cross state.The selection circuit 92 further receives the signal cmpr_FRD as thesignal for selecting the output signal. For example, the selectioncircuit 92 issues the signal “01” indicative of the cross state when thesignal cmpr_FRD is low (0), whereas it issues the signal “11” indicativeof the branch state when the signal cmpr_FRD is high (1).

The selection circuit 93 receives the 2-bit signal “00” indicative ofthe normal state and the 2-bit signal “01” indicative of the crossstate. The selection circuit 93 further receives the signal cmpr_FDFCOas the signal for selecting the output signal. For example, theselection circuit 93 issues the signal “01” indicative of the crossstate when the signal cmpr_FDFCO is low (0), whereas it issues thesignal “00” indicative of the normal state when the signal cmpr_FDFCO ishigh (1).

The selection circuit 94 receives the 2-bit signal “00” indicative ofthe normal state and the 2-bit signal “01” indicative of the crossstate. The selection circuit 94 further receives the signal cmpr_RDRCOas the signal for selecting the output signal. For example, theselection circuit 94 issues the signal “01” indicative of the crossstate when the signal cmpr RDRCO is low (0), whereas it issues thesignal “00” indicative of the normal state when the signal cmpr_RDRCO ishigh (1).

The selection circuit 95 receives the signals fed from the selectioncircuits 93 and 94. The selection circuit 95 further receives the signalcmpr_FD as the signal for selecting the output signal. For example, theselection circuit 95 issues the signal fed from the selection circuit 94when the signal cmpr_FD is low (0), whereas it issues the signal fedfrom the selection circuit 93 when the signal cmpr_FD is high (1).

The selection circuit 96 receives the signals fed from the selectioncircuits 91, 92, and 95. The selection circuit 96 further receives thesignal STATE of 2 bits as the signal for selecting the output signal.For example, the selection circuit 96 issues the signal fed from theselection circuit 91 when the signal STATE is “00” (0), issues thesignal fed from the selection circuit 92 when the signal STATE is “01”(1), and issues the signal fed from the selection circuit 95 when thesignal STATE is “11” (3). The signal issued from the selection circuit96 is the signal n_STATE.

The signals issued from the selection circuit 96 are fed to a data inputof the register 97. The signal change_mode and the clock signal CLK arefed to the AND circuit 98 whose output is provided to a clock input ofthe register 97. Thus, the signal n_STATE from the selection circuit 96is delivered to the register 97 at the timing when the signalchange_mode changes from low to high for example. The register 97 iscomprised of the gated clock, and the signal STATE changes at the nexttiming when the clock signal CLK changes from low to high.

FIG. 9 depicts an exemplary configuration of the decode circuit A 54.The decode circuit A 54 is configured to include selection circuits 101and 102, registers 103 and 104, XOR circuits 105 to 108, NOR circuits109 and 110, and an AND circuit 111.

The selection circuit 101 receives the signals N_FD and N_RD, as well asthe signal FCO issued from the register 103. The selection circuit 101receives the signal n_STATE as the signal for selecting the outputsignal. For example, the selection circuit 101 issues the signal N_FDwhen the signal n_STATE is “00” (0), issues the signal N_RD when thesignal n_STATE is “01” (1), and issues the signal FCO when the signaln_STATE is “11 (3).

The selection circuit 102 receives the signals N_FD and N_RD, as well asthe signal RCO issued from the register 104. The selection circuit 102receives the signal n_STATE as the signal for selecting the outputsignal. For example, the selection circuit 102 issues the signal N_RDwhen the signal n_STATE is “00” (0), issues the signal N_FD when thesignal n_STATE is “01” (1), and issues the signal RCO when the signaln_STATE is “11” (3).

The signals issued from the selection circuit 101 are fed to a datainput of the register 103. The signals issued from the selection circuit102 are fed to a data input of the register 104. The signal change_modeand the clock signal CLK are fed to the AND circuit 111 whose output isprovided to clock inputs of the registers 103 and 104. Thus, at thetiming when the signal change_mode changes from low to high for example,the signals from the selection circuit 101 are delivered to the register103 while the signals from the selection circuit 102 are delivered tothe register 104. The registers 103 and 104 are each comprised of thegated clock, and the signals FCO and RCO issued from the registers 103and 104, respectively, are changed at the next timing when the clocksignal CLK changes from low to high.

The XOR circuits 105 and 106, and the NOR circuit 109 are circuitscomparing the signal N_FD with the signal FCO, the NOR circuit 109issuing the signal cmpr_FDFCO indicative of the result of comparison. Inthis embodiment, the signal cmpr_FDFCO goes high when the signals N_FDand FCO are the same, whereas the signal cmpr_FDFCO goes low when theyare different.

The XOR circuits 107 and 108, and the NOR circuit 110 are circuitscomparing the signal N_RD with the signal RCO, the NOR circuit 110issuing the signal cmpr_RDRCO indicative of the result of comparison. Inthis embodiment, the signal cmpr_RDRCO goes high when the signals N_RDand RCO are the same, whereas the signal cmpr_RDRCO goes low when theyare different.

FIG. 10 depicts an exemplary configuration of the decode circuit B 55.The decode circuit B 55 is configured to include AND circuits 121 to127, OR circuits 128 and 129, and registers 130 to 133.

The AND circuit 121 receives the 0th bit of the signal n_STATE and theinversion of the 1st bit of the signal n_STATE. Thus, the output of theAND circuit 121 goes to “1” when the signal n_STATE is “01” (crossstate). The AND circuit 122 receives the 1st bit of the signal n_STATEand the inversion of the signal cmpr_FDFCO. Thus, the output of the ANDcircuit 122 goes to “1” when the signal n_STATE is “11” (branch state)and when the signal N_FD indicative of the sound source of the frontoutput changed is different from the signal FCO that is a selectionsignal for the analog selector 31. The outputs from the AND circuits 121and 122 are provided to the OR circuit 128 whose output is fed to a datainput of the register 130.

The AND circuit 123 receives the 0th bit of the signal n_STATE and theinversion of the 1st bit of the signal n_STATE. Thus, the output of theAND circuit 123 goes to “1” when the signal n_STATE is “01” (crossstate). The AND circuit 124 receives the 1st bit of the signal n_STATEand the signal cmpr_FDFCO. Thus, the output of the AND circuit 124 goesto “1” when the signal n_STATE is “11” (branch state) and when thesignal N_FD indicative of the sound source of the front output changedis the same as the signal FCO that is a selection signal for the analogselector 31. The outputs from the AND circuits 123 and 124 are providedto the OR circuit 129 whose output is fed to a data input of theregister 131.

The AND circuit 125 receives the 1st bit of the signal n_STATE and theinversion of the signal cmpr_FDFCO. Thus, the output of the AND circuit125 goes to “1” when the signal n_STATE is “11” (branch state) and whenthe signal N_FD indicative of the sound source of the front outputchanged is different from the signal FCO that is a selection signal forthe analog selector 31. The output of the AND circuit 125 is provided toa data input of the register 132.

The AND circuit 126 receives the 1st bit of the signal n_STATE and thesignal cmpr_FDFCO. Thus, the output of the AND circuit 126 goes to “1”when the signal n_STATE is “11” (branch state) and when the signal N_FDindicative of the sound source of the front output changed is the sameas the signal FCO that is a selection signal for the analog selector 31.The output of the AND circuit 126 is provided to a data input of theregister 133.

The AND circuit 127 receives the signal change_mode and the clock signalCLK. The output of the AND circuit 127 is provided to clock inputs ofthe registers 130 to 133. Thus, at the timing when the signalchange_mode changes from low to high for example, the signals from theOR circuits 128 and 129 are delivered to the registers 130 and 131,respectively, while the signals from the AND circuits 125 and 126 aredelivered to the registers 132 and 133, respectively. The registers 130to 133 are each comprised of the gated clock, and the signals FSEL,RSEL, FPD, and RPD issued from the registers 130 to 133, respectively,are changed at the next timing when the clock signal CLK changes fromlow to high.

FIG. 11 is a timing chart of an exemplary operation of the controlcircuit 36. In the initial state, the state of selection is normal state(N) at time T1 so that the input 0 is provided as both the front outputand the rear output.

When a control signal to provide the input 2 as the rear output is sentfrom the microcontroller 21 at time T3, the decode circuit 61 issues aselection signal “10” (2) and feeds a high signal to the rear changeenable signal. When the rear change enable signal goes high (1), thesignal N_RD issued from the selection circuit 67 turns to the selectionsignal “10” (2) from the decode circuit 61. At that time, the signalD_RD issued from the register 63 is “00” (0), allowing the signalcmpr_RD to go low.

At this timing, the selection signal “10” (2) is delivered to theregister 63. Since the front change enable signal is low (0), the signalN_FD issued from the selection circuit 66 is the signal D_FD, with thesignal cmpr_FD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are different, so that the signalcmpr_FRD goes low.

Due to the signal cmpr_FRD being low (0) with the signal STATE of “00”(NORMAL), the signal n_STATE remains unchanged, i.e., keeps “00”(NORMAL).

Since the signal n_STATE is “00” (0), the signal issued from theselection circuit 101 is the signal N_FD so that “00” is delivered tothe register 103. Similarly, the signal issued from the selectioncircuit 102 is N_RD so that “10” is delivered to the register 104. Thesignal N_RD is “10” with the signal RCO of “00” issued from the register104, allowing the signal cmpr_RDRCO to go low. The signal n_STATE is“00” and the signal cmpr_FDFCO is high, so that “0” is fed to theregisters 130 to 133.

Afterward, at time T4, the signal D_RD issued from the register 63 goesto “10” (2). In response to this, the signal cmpr_RD goes high and thesignal change_mode goes low. The signal RCO issued from the register 104goes to “10” (2), in response to which the signal cmpr_RDRCO goes high.Since the signal n_STATE is “00” (NORMAL) at time T3, the signal STATEremains “00” (NORMAL). All of the signals FSEL, FPD, RSEL, and RPD thengo to “0” so that the input 0 selected by the analog selector 31 isprovided as the front output and that the input 2 selected by the analogselector 32 is provided as the rear output.

In this manner, when changing over the rear output to a different soundsource from that of the front output in the state (normal state) wherethe front output and the rear output are different, switching of theanalog selector 31 is not carried out, so that no noise arises on thefront output side.

When a control signal to provide the input 2 as the front output is thensent from the microcontroller 21 at time T6, the decode circuit 61issues a selection signal “10” (2) and feeds a high signal to the frontchange enable signal. When the front change enable signal goes high (1),the signal N_FD issued from the selection circuit 66 turns to theselection signal “10” (2) from the decode circuit 61. At that time, thesignal D_FD issued from the register 62 is “00” (0), allowing the signalcmpr_FD to go low.

At this timing, the selection signal “10” (2) is delivered to theregister 62. Since the rear change enable signal is low (0), the signalN_RD issued from the selection circuit 67 is the signal D_RD, with thesignal cmpr_RD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are the same, so that the signalcmpr_FRD goes high.

Due to the signal cmpr_FRD being high (1) with the signal STATE of “00”(NORMAL), the signal n_STATE goes to “11” (BRANCH).

Since the signal n_STATE is “11” (3), the signal issued from theselection circuit 101 is the signal FCO so that “00” is delivered to theregister 103. Similarly, the signal issued from the selection circuit102 is the signal RCO so that “10” is delivered to the register 104. Thesignal N_FD is “10” with the signal FCO of “00” issued from the register103, allowing the signal cmpr_FDFCO to go low. The signal n_STATE is“11” and the signal cmpr_FDFCO is low, so that “1” is fed to theregisters 130 and 132 with “0” fed to the registers 131 and 133.

Afterward, at time T7, the signal D_FD issued from the register 62 goesto “10” (2). In response to this, the signal cmpr_FD goes high and thesignal change_mode goes low. Since the signal n_STATE is 11 (BRANCH) attime T6, the signal STATE goes to “11” (BRANCH). When the signal STATEgoes to “11” (3), the signal n_STATE goes to “01” (CROSS) since thesignal cmpr_FD is high (1) with the signal cmpr_FDFCO being low (0).Then, the signals FSEL and FPD go to “1” while the signals RSEL and RPDgo to “0”. Thus, the input 2 selected by the analog selector 32 isprovided as the front output and as the rear output, with the resultthat the operation of the ADC 33 becomes powered down.

Thus, when changing over the front output to the same sound source asthat of the rear output from the state (normal state) where the frontoutput and the rear output are different, the analog selectors 31 and 32do not select the same sound source so that no noise arises on the rearoutput side. Due to the operation of the ADC 33 becoming powered down,the power consumption can be reduced.

When a control signal to provide the input 3 as the rear output is thensent from the microcontroller 21 at time T9, the decode circuit 61issues a selection signal “11” (3) and feeds a high signal to the rearchange enable signal. When the rear change enable signal goes high (1),the signal N_RD issued from the selection circuit 67 turns to theselection signal “11” (3) from the decode circuit 61. At that time, thesignal D_RD issued from the register 63 is “10” (2), allowing the signalcmpr_RD to go low.

At this timing, the selection signal “11” (3) is delivered to theregister 63. Since the front change enable signal is low (0), the signalN_FD issued from the selection circuit 66 is the signal D_FD, with thesignal cmpr_FD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are different, so that the signalcmpr_FRD goes low.

Due to the signal cmpr_FRD being low (0) and the signal cmpr_FD beinghigh (1) with the signal STATE of “11” (BRANCH), the signal n_STATEremains “01” (CROSS).

Since the signal n_STATE is “01” (1), the signal issued from theselection circuit 101 is the signal N_RD so that “11” is delivered tothe register 103. On the other hand, the signal issued from theselection circuit 102 is the signal N_FD so that “10” is delivered tothe register 104. The signal N_RD is “11” with the signal RCO of “10”issued from the register 104, allowing the signal cmpr_RDRCO to go low.The signal n_STATE is “01” and the signal cmpr_FDFCO is low, so that “1”is fed to the registers 130 and 131 with “0” fed to the registers 132and 133.

Afterward, at time T10, the signal D_RD issued from the register 63 goesto “11” (3). In response to this, the signal cmpr_RD goes high and thesignal change_mode goes low. At this timing, the signal FCO issued fromthe register 103 goes to “11” (3). Since the signal n_STATE is “01”(CROSS) at time T9, the signal STATE goes to “01” (CROSS). Then, thesignals FSEL and RSEL go to “1” while the signals FPD and RPD go to “0”.Thus, the input 3 selected by the analog selector 31 is provided as therear output and the input 2 selected by the analog selector 32 isprovided as the front output.

Thus, when changing over the rear output to a different sound sourcefrom that of the front output from the state (branch state) where thefront output and the rear output are the same, the analog selector 32currently selecting the front output need not be switched, with theresult that no noise arises on the front output side.

When a control signal to provide the input 1 as the front output is thensent from the microcontroller 21 at time T12, the decode circuit 61issues a selection signal “01” (1) and feeds a high signal to the frontchange enable signal. When the front change enable signal goes high (1),the signal N_FD issued from the selection circuit 66 turns to theselection signal “01” (1) from the decode circuit 61. At that time, thesignal D_FD issued from the register 62 is “10” (2), allowing the signalcmpr_FD to go low.

At this timing, the selection signal “01” (1) is delivered to theregister 62. Since the rear change enable signal is low (0), the signalN_RD issued from the selection circuit 67 is the signal D_RD, with thesignal cmpr_RD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are different, so that the signalcmpr_FRD remains low.

Due to the signals cmpr_FRD and cmpr_FD being both low (0) with thesignal STATE of “01” (CROSS), the signal n_STATE still keeps “01”(CROSS).

Since the signal n_STATE is “01” (1), the signal issued from theselection circuit 101 is the signal N_RD so that “11” is delivered tothe register 103. On the other hand, the signal issued from theselection circuit 102 is the signal N_FD so that “01” is delivered tothe register 104. The signal n_STATE is “01” and the signal cmpr_FDFCOis low, so that “1” is fed to the registers 130 and 131 with “0” fed tothe registers 132 and 133.

Afterward, at time T13, the signal D_FD issued from the register 62 goesto “01” (1). In response to this, the signal cmpr_FD goes high and thesignal change_mode goes low. The signal RCO issued from the register 104goes to “01” (1). Since the signal n_STATE is “01” (CROSS) at time T12,the signal STATE still keeps “01” (CROSS). Then, the signals FSEL andRSEL remains “1” while the signals FPD and RPD remains “0”. Thus, theinput 3 selected by the analog selector 31 is provided as the rearoutput and the input 1 selected by the analog selector 32 is provided asthe front output.

Thus, when changing over the front output to a different sound sourcefrom that of the rear output in the state (cross state) where the frontoutput and the rear output are different, switching of the analogselector 31 does not occur, with the result that no noise arises on therear output side.

When a control signal to provide the input 3 as the front output is thensent from the microcontroller 21 at time T15, the decode circuit 61issues a selection signal “11” (3) and feeds a high signal to the frontchange enable signal. When the front change enable signal goes high (1),the signal N_FD issued from the selection circuit 66 turns to theselection signal “11” (3) from the decode circuit 61. At that time, thesignal D_FD issued from the register 62 is “01” (1), allowing the signalcmpr_FD to go low.

At this timing, the selection signal “11” (3) is delivered to theregister 62. Since the rear change enable signal is low (0), the signalN_RD issued from the selection circuit 67 is the signal D_RD, with thesignal cmpr_RD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are the same, so that the signalcmpr_FRD goes high.

Due to the signals cmpr_FRD being high (1) with the signal STATE of “01”(CROSS), the signal n_STATE goes to “11” (BRANCH).

Since the signal n_STATE is “11” (3), the signal issued from theselection circuit 101 is the signal FCO so that “11” is delivered to theregister 103. Similarly, the signal issued from the selection circuit102 is the signal RCO so that “01” is delivered to the register 104.Since the signal N_FD is “11” with the signal FCO of “03” issued fromthe register 103, the signal cmpr_FDFCO goes high. The signal n_STATE is“11” and the signal cmpr_FDFCO is high, so that “0” is fed to theregisters 130 and 132 with “1” fed to the registers 131 and 133.

Afterward, at time T16, the signal D_FD issued from the register 62 goesto “11” (3). In response to this, the signal cmpr_FD goes high and thesignal change_mode goes low. Since the signal n_STATE is “11” (BRANCH)at time T15, the signal STATE goes to “11” (BRANCH). Then, when thesignal STATE goes to “11” (3), the signal n_STATE goes to “00” (NORMAL)due to both the signals cmpr_FD and cmpr_FDFCO being high (1). Thesignals FSEL and FPD go to “0” while the signals RSEL and RPD go to “1”.Thus, the input 3 selected by the analog selector 31 is provided as thefront output and as the rear output so that the operation of the ADC 34becomes powered down.

Thus, when changing over the front output to the same sound source asthat of the rear output from the state (cross state) where the frontoutput and the rear output are different, the analog selectors 31 and 32do not select the same sound source, with the result that no noisearises on the rear output side. Due to the operation of the ADC 34becoming powered down, the power consumption can be reduced.

When a control signal to provide the input 0 as the rear output is thensent from the microcontroller 21 at time T18, the decode circuit 61issues a selection signal “00” (0) and feeds a high signal to the rearchange enable signal. When the rear change enable signal goes high (1),the signal N_RD issued from the selection circuit 67 turns to theselection signal “00” (0) from the decode circuit 61. At that time, thesignal D_RD issued from the register 63 is “11” (3), allowing the signalcmpr_RD to go low.

At this timing, the selection signal “00” (0) is delivered to theregister 63. Since the front change enable signal is low (0), the signalN_FD issued from the selection circuit 66 is the signal D_FD, with thesignal cmpr_FD being high. Thus, the signal change_mode goes high. Thesignal N_FD and the signal N_RD are different, so that the signalcmpr_FRD goes low.

Due to both the signals cmpr_FD and cmpr_FDFCO being high (1) with thesignal STATE of “11” (BRANCH), the signal n_STATE goes to “00” (NORMAL).

Since the signal n_STATE is “00” (0), the signal issued from theselection circuit 101 is the signal N_FD so that “11” is delivered tothe register 103. Similarly, the signal issued from the selectioncircuit 102 is the signal N_RD so that “00” is delivered to the register104. The signal n_STATE is “00” and the signal cmpr_FDFCO is high, sothat “0” is fed to the registers 130 to 133.

Afterward, at time T19, the signal D_RD issued from the register 63 goesto “00” (0). In response to this, the signal cmpr_RD goes high and thesignal change_mode goes low. Since the signal n_STATE is “00” (NORMAL)at time T18, the signal STATE goes to “00” (NORMAL). Then, all thesignals FSEL, FPD, RSEL, and RPD go to “0” so that the input 3 selectedby the analog selector 31 is provided as the front output while theinput 0 selected by the analog selector 32 is provided as the rearoutput.

Thus, when changing over the rear output to a different sound sourcefrom that of the front output from the state (branch state) where thefront output and the rear output are the same, the analog selector 31currently selecting the front output need not be switched, with theresult that no noise arises on the front output side.

==Example of Programmed Implementation==

Description will then be made of the case of providing a programmedcontrol for the signal selecting circuit 10. FIG. 12 depicts anexemplary configuration of the control circuit 36 in case of providingthe programmed control for the signal selecting circuit 10. The controlcircuit 36 is configured to include a processor 151, a ROM (Read OnlyMemory) 152, a RAM (Random Access Memory) 153, a first interface (firstI/F) 154, and a second interface (second I/F) 155.

The processor 151 reads and executes a program stored in the ROM 152, tothereby provide a control, etc., for the analog selectors 31 and 32, theADCs 33 and 34, and the digital selector 35. An area to store theprogram is not limited to the ROM 152 but may be any nonvolatile storagearea. A program read from an external nonvolatile memory area may bestored in a volatile memory area such as the RAM, for use. The RAM 153stores temporary data, etc., used by the processor 151. An area to storethe data is not limited to the RAM 153 but may be any writable memoryarea. The first I/F 154 serves to accept a control signal sent via themicrocontroller I/F 11 from the microcontroller 21. The second I/F 155serves to sent a control signal generated by the processor 151 to theanalog selectors 31 and 32, the ADCs 33 and 34, and the digital selector35.

FIG. 13 is a flowchart of operations of the control circuit 36. Theprocessor 151 checks whether a control signal is received from themicrocontroller 21 (S1301). When receiving the control signal (S1301:Y),the processor 151 checks whether either the front output or the rearoutput should be changed (S1302). If neither of the outputs should bechanged (S1302:N), then the processor 151 does not perform a changingoperation, returning to the control signal checking operation (S1301).

If either the front output or the rear output should be changed(S1302:Y), then the processor 151 checks whether the front output shouldbe changed (S1303). If affirmative, i.e., if the front output should bechanged (S1303:Y), then processor 151 sets a selection signal afterchange specified by the control signal sent from the microcontroller 21as a variable N_FDSP indicative of the front output after change andsets the value of a variable D_RDSP indicative of the current rearoutput stored in the RAM 153 as a variable N_RDSP indicative of the rearoutput after change (S1304). If negative, i.e., if the rear outputshould be changed (S1303:N), then processor 151 sets as the variableN_RDSP a selection signal after change specified by the control signalsent from the microcontroller 21 and sets as the variable N_FDSP thevalue of the variable D_FDSP indicative of the current front outputstored in the RAM 153 (S1305).

The processor 151 then checks a variable STATE indicative of the currentstate of selection stored in the RAM 153 (S1306). If the current stateof selection is normal state (S1306:NORMAL), then the processor 151checks whether the front output and the rear output are the same afterchange (S1306). If negative, i.e., if the front output and the rearoutput are different after change (S1306: N), then the processor 151updates the state of selection to the normal state (S1307). Theprocessor 151 then sets the control signals (FPD, RPD, FSEL, RSEL) to(0, 0, 0, 0), respectively (S1308), and sets the control signals (FCO,RCO) to (N_FDSP, N_RDSP), respectively (S1309). The control signals FPD,RPD, FSEL, and RSEL are fed to the ADCs 33 and 34 and the digitalselector 35 while the control signals FCO and RCO are fed to the analogselectors 31 and 32. The processor 151 sets the value of the variableN_FDSP as the variable D_FDSP and sets the value of the variable N_RDSPas the variable D_RDSP (S1310).

On the contrary, if the front output and the rear output are the sameafter change (S1306:Y), then the processor 151 updates the state ofselection to the branch state (S1311). The processor 151 then checkswhether the front output after change is the same as the current outputof the analog selector 31 (S1312). If affirmative, i.e., if the frontoutput after change is the same as the current output of the analogselector 31 (S1312:Y), then the processor 151 sets the control signals(FPD, RPD, FSEL, RSEL) to (0, 1, 0, 1), respectively (S1313). In thiscase, the operation of the ADC 34 is powered down so that the output ofthe analog selector 31 is provided as the front output and as the rearoutput. If the front output after change is different from the currentoutput of the analog selector 31, i.e., if the front output after changeis the same as the current output of the analog selector 32 (S1312:N),then the processor 151 sets the control signals (FPD, RPD, FSEL, RSEL)to (1, 0, 1, 0), respectively (S1314). In this case, the operation ofthe ADC 33 is powered down so that the output of the analog selector 32is provided as the front output and as the rear output. The processor151 outputs the control signals (FCO, RCO) intactly without changing(S1315). The processor 151 then updates the variables D_FDSP and D_RDSP(S1310). In this manner, when changing the state from the state (normalstate) where the front output and the rear output are different to thestate where they are the same, control is provided by switching thedigital selector 35 instead of selecting the same signal by the analogselectors 31 and 32. This prevents occurrence of a noise due to theselection of the same signal by the analog selectors 31 and 32 andpropagation of the noise to the side not changing the output.

If the state of selection is the branch state (S1306:BRANCH) when thecontrol signal is received, then the processor 151 checks whether thefront output should be changed (S1316). If the front output should notbe changed, i.e., if the rear output should be changed (S1316:Y), thenthe processor 151 checks whether the front output is the same as thecurrent output of the analog selector 31 (S1317). If affirmative, i.e.,if the front output is the same as the current output of the analogselector 31 (S1317:Y), then the processor 151 executes the aboveprocesses (S1307 to S1310). In this case, the state of selectiontransitions to the normal state.

On the contrary, if the front output is different from the currentoutput of the analog selector 31, i.e., if the front output is the sameas the current output of the analog selector 32 (S1317:N), then theprocessor 151 updates the state of selection to the cross state (S1318).The processor 151 then sets the control signals (FPD, RPD, FSEL, RSEL)to (1, 1, 0, 0), respectively (S1319), and sets the control signals(FCO, RCO) to (N_RDSP, N_FDSP), respectively (S1320). Then, the controlsignals FPD, RPD, FSEL, and RSEL are fed to the ADCs 33 and 34 and thedigital selector 35, while the control signals FCO and RCO are fed tothe analog selectors 31 and 32. The processor 151 updates the variablesD_FDSP and D_RDSP (S1310). In this case, the output of the analogselector 32 is provided as the front output, while the output of theanalog selector 31 is provided as the rear output. Thus, by enabling thestate of selection to transition from the branch state to the crossstate, the analog selector 31 or 32 associated with unchanged one of thefront and rear outputs need not be switched so that the unchanged outputis not subjected to a noise attendant on the switching of the other.

If the front output should be changed in the branch state (S1316:N),then the processor 151 checks whether the rear output is the same as thecurrent output of the analog selector 32 (S1321). If affirmative, i.e.,if the rear output is the same as the current output of the analogselector 32 (S1321:Y), then the processor 151 executes the aboveprocesses (S1307 to S1310). In this case, the state of selectiontransitions to the normal state.

On the contrary, if the rear output is different from the current outputof the analog register 32, i.e., if the rear output is the same as thecurrent output of the analog register 31 (S1321:N), then the processor151 executes the above processes (S1318 to S1320, and S1310). Thus, thestate of selection transitions to the cross state. In this case also,the analog selector 31 or 32 associated with unchanged one of the frontand rear outputs need not be switched so that the unchanged output isnot subjected to a noise attendant on the switching of the other.

If the state of selection is cross state when the control signal isreceived (S1306:CROSS), then the processor 151 checks whether the frontoutput and the rear output are the same after change (S1322). Ifnegative, i.e., if the front output and the rear output are differentafter change (S1322:N), then the processor 151 executes the aboveprocesses (S1318 to S1320 and S1310). In this case, the state ofselection remains the cross state.

On the contrary, if the front output and the rear output are the sameafter change (S1322:Y), then the processor 151 executes the aboveprocesses (S1311 to S1315 and S1310). That is, the state of selectiontransitions to the branch state. In this manner, when changing the stateof selection from the state (cross state) where the front output and therear output are different to the state where they are the same, controlis provided by switching the digital selector 35 instead of selectingthe same signal by the analog selectors 31 and 32. This preventsoccurrence of a noise due to the selection of the same signal by theanalog selectors 31 and 32 and propagation of the noise to the side notchanging the output.

Description has been made of the vehicle-mounted audio reproductioncircuit 1 configured to use the signal selecting circuit 10 of thisembodiment. As described above, the signal selecting circuit 10 enablesthe state of selection to transition from the normal state to the branchstate. That is, in case of changing over one of the front output and therear output to the same sound source as that of the other from the state(normal state) where the front output and the rear output are different,the output can be changed over by switching the digital selector 35without switching the analog selectors 31 and 32. Thus, since the analogselectors 31 and 32 do not select the same sound source, the noisecannot propagate to the unchanged output.

The signal selecting circuit 10 enables the state of selection totransition from the branch state to the cross state. That is, in case ofchanging over the front output to a different sound source from that ofthe rear output from the state (branch state) where a sound sourceselected by the analog selector 31 is provided as the front output andas the rear output, another sound source newly selected by the analogselector 32 is provided as the front output, with the sound sourceselected by the analog selector 31 being provided intactly as the rearoutput. Thus, since the analog selector 31 is not switched, a noise doesnot appear in the rear output. In case of changing over the rear outputfrom the state (branch state) where a sound source selected by theanalog selector 32 is provided as the front output and as the rearoutput, another sound source newly selected by the analog selector 31 isprovided as the rear output, with the sound source selected by theanalog selector 32 being provided intactly as the front output. Thus,since the analog selector 32 is not switched, a noise does not appear inthe front output.

The signal selecting circuit 10 enables the state of selection totransition from the cross state to the branch state. That is, in case ofchanging over one of the front output and the rear output to the samesound source as that of the other from the state (cross state) where thefront output and the rear output are different, the output can bechanged over by switching the digital selector 35 without switching theanalog selectors 31 and 32. Thus, since the analog selectors 31 and 32do not select the same sound source, the noise cannot propagate to theunchanged output.

The signal selecting circuit 10 enables the state of selection totransition from the cross state to the cross state. In this case, theanalog selector 31 or 32 selecting the unchanged output is not switchedso that no noise appears in the unchanged output.

The signal selecting circuit 10 enables the state of selection totransition from the branch state to the normal state. In this case, theanalog selector 31 or 32 selecting the unchanged output is not switchedso that no noise appears in the unchanged output.

The signal selecting circuit 10 enables the state of selection totransition from the normal state to the normal state. In this case, theanalog selector 31 or 32 selecting the unchanged output is not switchedso that no noise appears in the unchanged output.

The signal selecting circuit 10 enables the operation of one of the ADCs33 and 34 to be powered down in the branch state. This achieves areduction in the power consumption of the signal selecting circuit 10.Although the operation of one of the ADCs 33 and 34 is powered down inthis embodiment, the operation of one of the analog selectors 31 and 32may be powered down in lieu of the ADCs 33 and 34.

The above embodiment of the present invention is simply for facilitatingthe understanding of the present invention and is not in any way to beconstrued as limiting the present invention. The present invention mayvariously be changed or altered without departing from the spiritthereof and encompasses equivalents thereof.

For example, although the signal selecting circuit 10 is applied to thevehicle-mounted audio reproduction circuit 1 by way of example in thisembodiment, application of the signal selecting circuit 10 is notlimited thereto. For example, an audio reproduction circuit may beconfigured that is capable of outputting the same sound source ordifferent sound sources to speakers disposed in a plurality of rooms.Although the number of the analog selectors receiving a plurality ofanalog signals is two, i.e., the analog selectors 31 and 32 in thisembodiment, three or more analog selectors may be employed. In case ofthe above audio reproduction circuit selecting sound sources outputtedto the plurality of rooms, a corresponding number of analog selectors tothe number of the rooms may be disposed to provide a control for each ofthe rooms.

1. A signal selecting circuit outputting a first and a second digitalsignals by converting a first and a second analog signals into digitalsignals, the first and the second analog signals being the same ordifferent signals selected from a plurality of analog signals, thesignal selecting circuit comprising: an analog signal selection circuitthat, based on an analog selection signal, selects the first and thesecond analog signals from the plurality of analog signals; a first ADconverter that converts the first analog signal outputted from theanalog signal selection circuit into a third digital signal to outputthe third digital signal; a second AD converter that converts the secondanalog signal outputted from the analog signal selection circuit into afourth digital signal to output the fourth digital signal; a digitalsignal selection circuit that, based on a digital selection signal,selectively outputs one or both of the third and the fourth digitalsignals as the first and the second digital signals; and a controlcircuit that, based on an output selection signal for selecting thefirst and the second digital signals, outputs the analog selectionsignal and the digital selection signal.
 2. The signal selecting circuitof claim 1, wherein when the control circuit receives the outputselection signal for changing the second digital signal to the samesignal as the first digital signal, in a state where the third digitalsignal is outputted as the first digital signal and where the fourthdigital signal is outputted as the second digital signal, the controlcircuit outputs the digital selection signal for outputting the thirddigital signal as the first and the second digital signals.
 3. Thesignal selecting circuit of claim 1, wherein when the control circuitreceives the output selection signal for changing the first digitalsignal to a signal different from the second digital signal, in a statewhere the third digital signal is outputted as the first and the seconddigital signals, the control circuit outputs the analog selection signalfor selecting as the second analog signal an analog signal correspondingto the first digital signal indicated by the output selection signal,without changing the first analog signal.
 4. The signal selectingcircuit of claim 1, wherein when the control circuit receives the outputselection signal for changing the first digital signal to the samesignal as the second digital signal, in a state where the third digitalsignal is outputted as the second digital signal and where the fourthdigital signal is outputted as the first digital signal, the controlcircuit outputs the digital selection signal for outputting the thirddigital signal as the first and the second digital signals.
 5. Thesignal selecting circuit of claim 1, wherein when the control circuitreceives the output selection signal for changing the first digitalsignal to a signal different from the second digital signal, in a statewhere the third digital signal is outputted as the second digital signaland where the fourth digital signal is outputted as the first digitalsignal, the control circuit outputs the analog selection signal forselecting as the second analog signal an analog signal corresponding tothe first digital signal indicated by the output selection signal,without changing the first analog signal.
 6. The signal selectingcircuit of claim 1, wherein when control circuit receives the outputselection signal for changing the second digital signal to a signaldifferent from the first digital signal, in a state where the thirddigital signal is outputted as the first and the second digital signals,the control circuit outputs: the analog selection signal for selectingas the second analog signal an analog signal corresponding to the seconddigital signal indicated by the output selection signal, withoutchanging the first analog signal; and the digital selection signal foroutputting the third digital signal as the first digital signal andoutputting the fourth digital signal as the second digital signal. 7.The signal selecting circuit of claim 1, wherein when the controlcircuit receives the output selection signal for changing the firstdigital signal to a signal different from the second digital signal, ina state where the third digital signal is outputted as the first digitalsignal and where the fourth digital signal is outputted as the seconddigital signal, the control circuit outputs the analog selection signalfor selecting as the first analog signal an analog signal correspondingto the first digital signal indicated by the output selection signal. 8.The signal selecting circuit of claim 2, wherein when outputting thedigital selection signal for outputting the third digital signal as thefirst and the second digital signals, the control circuit powers down anoperation of the second AD converter.
 9. The signal selecting circuit ofclaim 4, wherein when outputting the digital selection signal foroutputting the third digital signal as the first and the second digitalsignals, the control circuit powers down an operation of the second ADconverter.
 10. A recording medium having a program recorded thereon, theprogram causing a processor of a signal selecting circuit which includesthe processor that performs control for outputting a first and a seconddigital signals by converting a first and a second analog signals intodigital signals, the first and the second analog signals being the sameor different signals selected from a plurality of analog signals, ananalog signal selection circuit that, based on an analog selectionsignal, selects the first and the second analog signals from theplurality of analog signals, a first AD converter that converts thefirst analog signal outputted from the analog signal selection circuitinto a third digital signal to output the third digital signal, a secondAD converter that converts the second analog signal outputted from theanalog signal selection circuit into a fourth digital signal to outputthe fourth digital signal, a digital signal selection circuit that,based on a digital selection signal, selectively outputs one or both ofthe third and the fourth digital signals as the first and the seconddigital signals, and a memory that stores a state of selection of thethird and the fourth digital signals in the digital signal selectioncircuit, to execute the steps of: accepting an output selection signalfor selecting the first and the second digital signals; outputting theanalog selection signal and the digital selection signal based on theoutput selection signal accepted and on the state of selection stored inthe memory; and updating the state of selection stored in the memory.11. The recording medium having a program recorded thereon of claim 10,the program causing the processor, to execute the steps of: whenaccepting the output selection signal for changing the second digitalsignal to the same signal as the first digital signal, in a state wherethe third digital signal is outputted as the first digital signal andwhere the fourth digital signal is outputted as the second digitalsignal, outputting the digital selection signal for outputting the thirddigital signal as the first and the second digital signals; and updatingthe state of selection stored in the memory.
 12. The recording mediumhaving a program recorded thereon of claim 10, the program causing theprocessor, to execute the steps of: when accepting the output selectionsignal for changing the first digital signal to a signal different fromthe second digital signal, in a state where the third digital signal isoutputted as the first and the second digital signals, outputting theanalog selection signal for selecting as the second analog signal ananalog signal corresponding to the first digital signal indicated by theoutput selection signal, without changing the first analog signal; andupdating the state of selection stored in the memory.
 13. The recordingmedium having a program recorded thereon of claim 10, the programcausing the processor, to execute the steps of: when accepting theoutput selection signal for changing the first digital signal to thesame signal as the second digital signal, in a state where the thirddigital signal is outputted as the second digital signal and where thefourth digital signal is outputted as the first digital signal,outputting the digital selection signal for outputting the third digitalsignal as the first and the second digital signals; and updating thestate of selection stored in the memory.
 14. The recording medium havinga program recorded thereon of claim 10, the program causing theprocessor, to execute the step of, when accepting the output selectionsignal for changing the first digital signal to a signal different fromthe second digital signal, in a state where the third digital signal isoutputted as the second digital signal and where the fourth digitalsignal is outputted as the first digital signal, outputting the analogselection signal for selecting as the second analog signal an analogsignal corresponding to the first digital signal indicated by the outputselection signal, without changing the first analog signal.
 15. Therecording medium having a program recorded thereon of claim 10, theprogram causing the processor, to execute the steps of: when acceptingthe output selection signal for changing the second digital signal to asignal different from the first digital signal, in a state where thethird digital signal is outputted as the first and the second digitalsignals, outputting the analog selection signal for selecting as thesecond analog signal an analog signal corresponding to the seconddigital signal indicated by the output selection signal, withoutchanging the first analog signal, and the digital selection signal foroutputting the third digital signal as the first digital signal andoutputting the fourth digital signal as the second digital signal; andupdating the state of selection stored in the memory.
 16. The recordingmedium having a program recorded thereon of claim 10, the programcausing the processor, to execute the step of, when accepting the outputselection signal for changing the first digital signal to a signaldifferent from the second digital signal, in a state where the thirddigital signal is outputted as the first digital signal and where thefourth digital signal is outputted as the second digital signal,outputting the analog selection signal for selecting as the first analogsignal an analog signal corresponding to the first digital signalindicated by the output selection signal.
 17. The recording mediumhaving a program recorded thereon of claim 11, the program causing theprocessor to execute the step of outputting a signal for powering downan operation of the second AD converter, when outputting the digitalselection signal for outputting the third digital signal as the firstand the second digital signals.
 18. The recording medium having aprogram recorded thereon of claim 13, the program causing the processorto execute the step of outputting a signal for powering down anoperation of the second AD converter, when outputting the digitalselection signal for outputting the third digital signal as the firstand the second digital signals.